1. Field of the Invention
This invention relates generally to semiconductor fabrication, and more particularly to a tungsten gate electrode and methods of fabricating the same.
2. Description of the Related Art
Aluminum and doped polycrystalline silicon have been widely used for decades as gate electrode materials in MOS circuit designs. Indeed some of the earliest MOS integrated circuits were implemented as p-channel enhancement mode devices using aluminum as the gate electrode material. Aluminum became an early material of choice due to its relatively low resistivity and material cost. Furthermore, there was already a large body of manufacturing experience with aluminum in the chip industry developed from bipolar integrated circuit processing.
A later process innovation that is still widely used today, involves the use of heavily doped polysilicon as a gate electrode material in place of or as a complement to aluminum. The switch to polysilicon as a gate electrode material stemmed from a recognition on the part of process engineers of certain limitations associated with aluminum in early fabrication technologies. In conventional semiconductor fabrication processing, aluminum must be deposited following completion of all high temperature process steps (including drive-in of the source and drain regions). As a result, an aluminum gate electrode must ordinarily be separately aligned to the source and drain. This alignment procedure can adversely affect both packing density and parasitic overlap capacitances between the gate and source/drain regions. In contrast, polysilicon with its much higher melting point, can be deposited prior to source and drain formation and therefore provide for self-aligned gate processing. Furthermore, the high temperature capability of polysilicon is routinely exploited to enable interlevel dielectric layers to be applied to provide multiple metallization layers with improved planarity.
Despite the several advantages of polysilicon over aluminum as a gate electrode material, polysilicon has the disadvantage of a much higher resistivity as compared to aluminum. Higher resistivity translates into higher values of interconnect line resistance that can lead to undesirably long RC time constants and DC voltage variations within VLSI or ULSI circuits. The development of polycide films on top of polysilicon layers has alleviated some of the resistivity shortcomings of polysilicon gate electrodes. However, the resistivity of polysilicon gate electrodes in conventional MOS integrated circuit processing still presents a potential impediment to successful process scaling through reductions in the operating voltages of VLSI and ULSI devices.
Another disadvantage of polysilicon as a gate electrode material is polysilicon depletion. In p-channel transistors, the source and drain are commonly formed in the substrate by implanting a p-type dopant, such as boron. The implant also deposits boron into the polysilicon of the gate electrode. Subsequent thermal processing steps to fabricate a conventional p-channel field effect transistor frequently cause boron to diffuse from the gate electrode through the gate oxide layer and into the channel region. If the amount of boron diffused is sufficiently high, the electrical performance of the field effect transistor may be severely degraded due to polysilicon depletion.
Interest has recently turned to alternative materials, such as tungsten, for gate electrode design. The larger work function of tungsten produces low and nearly symmetrical threshold voltages for both PMOS and NMOS devices on moderately doped substrates. Accordingly, tungsten is attractive as a gate electrode material in CMOS circuit design. In addition, tungsten gate electrodes have the potential to exhibit reduced subthreshold leakage currents and decreased sensitivity to body bias as compared to conventional doped polysilicon gate electrodes. Finally, the resistivities of tungsten gate electrodes may be as much as 100 times or more lower than comparably sized doped polysilicon gates.
Despite the several advantages offered by tungsten as a gate electrode material, the integration of tungsten into semiconductor processing involves a number of significant challenges. In the conventional fabrication of a tungsten gate electrode stack, a gate oxide layer is formed on a doped silicon substrate by thermal oxidation or chemical vapor deposition ("CVD"). Thereafter, an adhesion or so-called "glue" layer is blanket deposited on the gate oxide layer. A tungsten film is next deposited on the glue layer. In many conventional processes, the tungsten film is deposited by the CVD reduction of WF.sub.6 in a silane ambient. The deposition of a glue layer is a necessary predicate to CVD tungsten deposition due to the relatively poor adhesion of CVD tungsten to oxide. Thus, a glue layer composed of a material which exhibits acceptable adhesion to the underlying oxide and the later-deposited tungsten film is applied as a precursor to the tungsten CVD step.
Titanium nitride is a common material used for a glue layer, although other titanium based films, such as Ti:W have been used as well. The deposition of a titanium based adhesion film normally cannot be carried out in the same CVD chamber used to deposit the CVD tungsten film. Accordingly, the CVD glue layer and the CVD tungsten films involve separate deposition steps in separate chambers and the attendant movement of wafers between the two.
Another shortcoming of conventional tungsten gate electrode stack processing stems from the highly reactive character of titanium and the chemistry associated with CVD tungsten. As noted above, many conventional CVD tungsten deposition processes involve the reduction of WF.sub.6 in silane. This reduction process liberates quantities of fluorine which may readily diffuse into the underlying titanium based adhesion film and react with the titanium therein. The incorporation of TiF.sub.X compounds into the adhesion layer may not only degrade the resistivity of the glue layer, but more significantly, may result in the ultimate delamination of the glue layer from the underlying oxide layer. This can produce not only undesirable device performance but also catastrophic device failure depending upon the extent of the delamination.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.